CPU in an intelligent electronic device is either in a working state or in a sleeping state. The sleeping state of CPU is usually classified as one of a variety of sleeping modes from light to deep, the deeper the sleeping mode is, the lower the power consumption is, and meanwhile the higher the price for awaking (awaking time, power consumption required for awaking). When detecting that there is nothing to do at present and preparing to put the CPU into a sleeping state, operating system will weigh a variety of factors, and put the CPU into an appropriate sleeping mode.
The sleeping modes of various models of CPU, although differing in amount and meaning, have substantially the same principle. OMAP4460 chip of Texas instruments (TI) company, for example, is a dual-core CPU having the kernel of ARM Cortex A9, and has four sleeping modes C1-C4. The operating system determines which sleeping mode the CPU may enter according to expected sleeping time, as shown in the following Table 1:
TABLE 1Four sleeping modes of OMAP4460 chipExpected sleeping timeSleeping modeFrom shallow to deep  >4 μs >1100 μs >1200 μs >1500 μsCl C2 C3 C4
OMAP4460 chip is just used as the CPU of the Google Galaxy Nexus cell phone, whose overall power consumption in addition to the display is listed as follows: 1 W in the working state; 0.62 W in the C1 sleeping mode; 0.15 W in the C2 sleeping mode; 0.12 W in the C3 sleeping mode; and 0.08 W in the C4 sleeping mode. Obviously, if the duration of CPU in the sleeping state can be prolonged while the system performance is guaranteed, or the sleep mode of CPU is changed from light to deep, the power consumption shall be reduced significantly.
In an intelligent electronic device with a single processor, the following three events may awake the CPU from the sleeping state to the working state:
1) CPU detects an external interrupt;
2) CPU detects an asynchronous abort event of an external device; and
3) CPU detects a debugging event, e.g. debugging of JTAG (Joint Test Action Group) or ICE (In-Circuit Emulator).
The interrupts are usually divided by the operating system into two major types, hardware interrupt and software interrupt, wherein the hardware interrupt is further divided into two minor types, external interrupt and internal interrupt. The external interrupt refers to an interrupt request from an external device (i.e. a hardware device in addition to the CPU and the memory). The interrupt controller is responsible for reporting the external interrupt to the CPU, with a programmable interrupt controller (PIC) currently widely used. An early interrupt controller is a hardware chip independently packaged separated from the CPU, while at present it is usually integrated with the CPU in one package.
An existing interrupt controller is as shown in FIG. 1. On one hand, it is connected to a plurality of external devices and receives the external interrupt from them; on the other hand, it is connected to the CPU and reports the external interrupts to the CPU, i.e. sending an interrupt signal to the CPU. Generally, the interrupt controller reports the external interrupt to the CPU immediately after receiving it. If a plurality of external interrupts occur simultaneously, the interrupt controller will report them one by one to the CPU according to the priority level. The CPU, once receiving the external interrupt, will call the corresponding interrupt processing function to process.
As shown in FIG. 2, the external interrupt is random in time, and the real-time reporting mechanism used in the interrupt controller is not based on whether the CPU is in working state or in sleeping state. The CPU in sleeping state, once receiving the interrupt signal, will be awaked into working state. Various external interrupts fragmentize the sleeping time of CPU, and make the CPU difficult to enter a deep sleeping mode.
A symmetric multi processor (SMP) system refers to that more than two processors are provided on one intelligent electronic device, and share resources such as memory and etc. The case in which a plurality of computing cores are gathered on one processor chip also belongs to the case of the SMP system, with each of the computing cores being regarded as a CPU. In the SMP system, in addition to the above three events, the CPU in the sleeping state will also be awaked back to the working state once it detects the memory consistency broadcast messages from other CPUs.
In the SMP system, each of the CPUs has an independent cache. A CPU, when modifying its own cache, will send memory coherency broadcast messages to other CPUs, telling other CPUs about this modification. Because the CPU makes very frequent modification to the cache, there are also frequent memory coherency broadcast messages.
As shown in FIG. 3, the memory coherency broadcast messages frequently occurring in the SMP system repeatedly awake a CPU in the sleeping state, with the CPU receiving the memory consistency broadcast messages even at the beginning of each sleep, and thus the CPU is awaked immediately; the awaked CPU will again enter the sleeping state in its spare time. This makes the sleeping time of each of the CPUs in the SMP system always very short, usually <10 μs.